The present invention relates generally to integrated circuit packages. More specifically, the present invention relates to miniature chip scale packages manufactured in wafer form and improved package structures.
With current emphasis on increased circuit density and decreased integrated circuit package footprints, process engineers attempt to design increasingly smaller and more dense integrated circuit packages. A current outgrowth of this emphasis is the chip scale package. Typically, a chip scale package has an overall package dimension that is relatively close to that of the integrated circuit die, or chip, that is enclosed within the package. Generally, chip scale packages are manufactured either using individual chips that have been singulated from a wafer, or in wafer form and then the individual chip scale packages are singulated from the wafer. The latter type of chip scale package is referred to as a wafer level chip scale package.
One example of a wafer level chip scale package is a surface mount die, such as a flip chip package. Surface mount dice typically have input/output contacts, such as solder bumps, that are located on the active surface of the die.
FIG. 1A is a diagrammatic side view of a conventional flip chip package. Typically, the flip chip package 100 includes a die 102 having a plurality of conventionally fabricated integrated circuit structures, such as transistors, etc. (not shown). The top surface of the die 102 includes contact pads 104 which provide for conductive interconnection to the integrated circuit structures of the die 102. Contact bumps 106, such as solder bumps, are conventionally formed on the contact pads 104 to allow for interconnection of the package to other substrates. The bottom surface of the die 102 is conventionally left bare. Typically, a plurality of flip chip packages 100 are formed on the surface of an integrated circuit wafer (not shown). After fabrication of the flip chip packages, the wafer is singulated into individual flip chip packages 100, for example, by laser cutting or sawing. The individual flip chips may then be inverted and attached to a substrate, such as a printed circuit board.
In attaching the flip chip to the substrate, the contact bumps are typically aligned and electrically coupled to an associated board contact of the substrate, for example, by a reflow process, which forms a solder joint. In this way, a high density of input/output pads are provided within a small package footprint as the contact pads are over the die itself. A disadvantage of this design is that stresses introduced on the contact bumps may damage the flip chip package.
FIG. 1B is a diagrammatic side view of a conventional flip chip package attached to a substrate. Typically, the die 102 of the flip chip package 100 and the substrate 110 are formed from different materials that may have substantially different coefficients of thermal expansion. When the flip chip contact bumps 106 are attached to the contact pads 108 of the substrate 110 and power is applied, the resultant heat dissipates in the die 102 and the substrate 110 causing each to expand and contract in different amounts. This causes the contact bumps 106, which are on the contact pads 104 of the die 102, to move relative to the contact pads 108 of the substrate 110.
As the solder joint in this design is a relatively rigid joint structure, the relative movement can deform and stress the contact bumps 106 and may ultimately result in damage to the flip chip package 100, for example, solder joint fatigue. Further, the stresses on the contact bumps 106 may push the contact bumps 106 into the underlying layers that form the die 102 and cause craters within the die 102. Additionally, the stresses may cause the contact bumps 106 to tear open.
To mitigate the effects of the stresses, an underfill layer 112 is typically injected between the substrate 110 and the flip chip package 100 and around the contact bumps 106 of the flip chip package 100. The underfill layer 112 helps to reduce the stress effects of the differential thermal expansion between the die 102 and the substrate 110 and to improve the reliability of the package. However, the addition of the underfill layer 112 results in an extra processing step and increased associated costs, thus impacting overall production costs and production yield. Additionally, as the contact bumps 106 and underfill layer 112 are rigidly attached to the die 102, the package 100 still retains some stress-related problems which can be transferred to and damage the die 102.
Further, the design of the package 100 restrains both the arrangement of the contact bumps 106 and the arrangement of the contact pads 108 of a substrate to the arrangement of the contact pads 104 on the die 102. Thus, this design tends to limit the packaging to use with smaller die sizes/pin counts, for example, 3xc3x973 mm size/28-40 leads.
In an attempt to mitigate the stresses and costs associated with the above-described package, another design, further described in U.S. Pat. No. 5,834,844 to Akagawa et al., describes a wafer level process for forming a chip sized semiconductor package that utilizes a circuit-patterned insulation sheet adhered to a semiconductor die. External contacts for connecting to a substrate are formed on the insulation sheet and are conductively connected to the die through the insulation sheet.
FIG. 2 is a diagrammatic side view of an example of a portion of a conventional semiconductor package utilizing a circuit-patterned insulation sheet adhered to a semiconductor die. The semiconductor package 200 includes an integrated circuit die 202, an insulation sheet 204 adhered to the die 202, a circuit pattern 206 formed on the insulation sheet 204, an electro-insulation layer 208 formed over the circuit pattern 206 and external contacts 210 connected to the circuit pattern 206.
The die 202 typically includes a plurality of conventionally fabricated integrated circuit structures. The top surface of the die 202 includes bond pads 212 that provide interconnection to the integrated circuit structures of the die 202. The die 202 further includes a passivation layer 214 having vias formed over the bond pads 212. A first side of the insulation sheet 204 is attached to the die 202 and the second side has circuit patterns 206 formed on it in a predetermined pattern. The insulation sheet 204 has vias located over the bond pads 212 that are filled with a conductive material to provide a conductive connection between the bond pads 212 and the circuit pattern 206. An electro-insulation layer 208 is formed to cover the insulation sheet 204 and the circuit patterns 206 and has vias formed in it over portions of the circuit pattern 206. Contact bumps 210 are formed within the vias and conductively contact the circuit pattern 206. Although the insulation sheet 204 may provide some stress absorption, the joint structure is still relatively rigid, and, as the insulation sheet 204 is adhered to the entire surface of the die 202, some of the stresses introduced at the contact bump 210 may still be passed on to the die 202.
Thus, there is a need for a wafer level fabricated chip scale integrated circuit package design having a more compliant connection that can mitigate stresses on the joint and can decouple the stresses from the die.
To achieve the foregoing, and in accordance with the purpose of the present invention, there are described wafer level chip scale integrated circuit package devices and methods for forming wafer level chip scale integrated circuit packages which provide highly compliant connections between external substrates and the packaged integrated circuit die, and, additionally, provide flexibility in locating the external contacts which may be connected to other substrates.
In one embodiment of the present invention, an integrated circuit package having compliant leads is described. The compliant leads are located over and conductively coupled to at least some of the bond pads on a die such that an air gap having a vertical distance is formed between the integrated circuit die and the compliant leads.
In another embodiment of the present invention, a wafer level method of packaging integrated circuits is described. In this embodiment, a sacrificial layer is deposited over the top surface of an integrated circuit wafer and vias are formed in the sacrificial layer over the bond pads on the various dice. Compliant leads are formed over the bond pads such that each of the compliant leads are conductively coupled to an associated bond pad through a via. The sacrificial layer is removed forming an air gap having a vertical distance between the integrated circuit wafer and the compliant leads. The integrated circuit wafer is then singulated into individual integrated circuit packages.
In another embodiment of the present invention, an integrated circuit wafer is described. A plurality of bond pads are located on the top surface of the integrated circuit wafer. A plurality of compliant leads are located over and conductively coupled to the plurality of bond pads such that an air gap having a vertical distance is formed between the compliant leads and the integrated circuit wafer.